Conventional metal-oxide silicon (“MOS”) capacitors include electrical contacts that are made to a metal gate of the capacitor structure and a back contact that is made to the semiconductor of the capacitor structure. A basic MOS capacitor operates using charge distributions in the capacitor structure. The three general types of charge distribution that occur include accumulation, depletion and inversion conditions. Accumulation typically results from a negative voltage being applied to the gate of the capacitor structure and depletion occurs from a positive voltage being applied to the gate. Inversion generally occurs at positive voltages that are larger than a threshold voltage.
An example of a representative layout of a microelectronic capacitor 100 is illustrated in FIG. 1 in which the capacitor 100 generally consists of two conductive plates that are separated by a dielectric layer. The dielectric layer may be silicon oxide and is sandwiched between the capacitor plates that are preferably made using doped crystalline silicon and a gate conductor. Contact to the gate conductor plate is established using a double row of contact-to-gate “CG” contacts 102 that are located at the middle of the rectangular capacitor structure. During operation, the double row of CG contacts provides a rectangular current flow.
The CG contacts 102 connect a first metallization layer with the conductive gate material. There is no crystalline silicon immediately underneath the CG contacts 102. Instead, an island of silicon oxide is situated underneath the CG contacts 102. Contact to the crystalline silicon plate is established using a plurality of contact-to-diffusion “CD” contacts 104. The CD contacts 104 connect the first metallization layer with the crystalline silicon surface or substrate. The CD contacts 104 are located at the circumference of the rectangular shaped capacitor.
Capacitor charging and discharging speed is dependent on the capacitance of the parallel-plate capacitor and also on the total internal resistance of the capacitor. The higher the total internal resistance, the slower the capacitor can be charged or discharged. The total internal resistance for a microelectronic capacitor consists of the CD contact resistance, the doped crystalline silicon resistance, the gate conductor resistance and the CG contact resistance. As such, the total internal capacitor resistance can be computed as follows: Rcapacitor, internal=RCD contacts+Rcrystal.Si+Rgate conductor+RCG contacts.
Based on the above-referenced equation, it can be determined that for the microelectronic capacitor layout set forth in FIG. 1, the component resistances have a contribution to the total internal resistance of the capacitor of the following percentages: RCD contacts=1.1%; Rcystal.Si=95.2%; Rgate conductor=3.6%; RCG contacts=0.1%. It can clearly be seen that the crystalline silicon has the largest contribution to the total internal capacitor resistance. Capacitor sizes range from a few um2 to several 1000 um2 and even larger dependent on the specific application and the total area of the capacitor needed for the CD contacts is about 7.4% and for the CG contacts 6.2%.
A problem with the current art of microelectronic capacitor layout is that the internal resistances are not optimized. The total internal resistance is also too high, which leads to unnecessary delays in the charging and discharging speed of capacitors in circuits. In order to optimize a microelectronic capacitor layout, it is not advisable to simply increase the number of CG and CD contacts. Such an increase would not only increase the total capacitor area but would also lead to only a minimal benefit in the total internal capacitor resistance. Alternatively, the crystalline silicon area could be split up in an attempt to minimize the current path through the crystalline silicon. However, this would lead to a substantial increase in the total capacitor area.
As such, a microelectronic capacitor layout is needed that reduces the total internal resistance of the capacitor and the area needed to manufacture the capacitor on the silicon substrate.